Intel introduces Haswell processor

Right at the beginning of the IDF Intel pumping properly, it can, with the new processor generation Haswell. After product chief Daddi Permutter in his opening speech vorführte a demo in which a prototype Haswell delivered with the same power consumption about twice the performance as a current model, presented chief architect Ronak Singhal and his crew to incorporate it in more detail. Its extensions in the instruction set (AVX2, FMA and TSX) Intel had already given some time known in advance, now followed by details on the hardware architecture.

Outstanding here is the new active state power management "S0ix active idle", the down reduces energy consumption while doing nothing on the economical level of the sleep states S3 or S4, but does not require a long recovery time (Resume). All this is done automatically by hardware in fine-grained levels. There are also numerous improvements, both in the active state and in the S3/S4-Schlafzuständen. The CPU cores themselves offer for new C-States. The transition times were accelerated by 25 percent and the links to Periphie have new power management states. The platforms will display with Auto Refresh (PSR) have so that ultimately the power consumption can be reduced in idle to one-twentieth of the current values​​.


To increase the performance of Intel Haswell when compared to Ivy Bridge considerably knitted at the micro-architecture, but without changing the basic pipeline. Increases, the bandwidth to fetch the code, the branch prediction has been improved and enlarged the window for out-of-order. The L2 TLB is now slightly larger and optimized for large memory pages. Above all there were two additional ports that are served from the reservation station: Port 6 provides a fourth integer ALU and an additional branch unit. Port 7 controls to a dedicated store-address unit. The mighty AVX2 command for multiply-add (FMA) can be performed in parallel in two units via Port 0 and 1 with a latency of 5 cycles. In throughput Haswell comes with twice FMA at 32 flops per clock and core in single-precision and 16 flops / clock / core in the double precision, so it is likely the major Linpack benchmark at the same clock and the same number of nuclei twice the performance compared to the current Ivy Bridge reach.

That's enough alone to summon more functional units, the data must also be replenished fast enough. These Intel has doubled the L1 data and L2 cache throughput. The L1D can now read and write 64 bytes per clock (two AVX-words), and 32 bytes.

With the graphics Intel has the GT3 risen alongside numerous detail improvements, a second "wheel" to GT2: doubling the number of execution units (shaders), as well as units for rasterization, Z, stencil, color fade, and so on as well as the overall size of caches. The second disk can be turned off to save energy. The common "Not long" show part of the front pipeline sit include the Fix function units whose performance was doubled for most rendering tasks also. Finally, there is still the part of media, now offers the scalable video coding (SVC), and Motion-JPEG decoders. For MPEG2 can encode it on the fly, for example DLNA streaming and DVD production. It also now supports the playback of 4Kx2K video. While at Ivy Bridge, the individual engines could double work in parallel with the Haswell codec engines, imaging and scale / composite can now work in a triple parallel.

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