Intel is reportedly planning processors with integrated graphics memory
The performance of onboard graphics, today usually built right into the CPU is relatively small. Three major factors limit the GPU aka GPU: It may prove cost reasons only a certain portion of the total chip area, so it has fewer transistors than the GPU on a graphics card. Moreover, his thirst for power and capped it must share the main memory with the CPU cores and the PCI Express Root Complex.
Modern processors contain CPU and GPU cores, PCIe connectivity and memory controller. The latter controls often two each 8 bytes wide to DDR3-SDRAM channels with up to 800 MHz (DDR3-1600). Hence s data transfer rate of nearly 26 GB / High-end graphics chips for example, 256 data signal lines (32 bytes) to GDDR5 SDRAM, 2.5 GHz, data Read-/Write-Clock but with up to 160 GB / s read or write. Through these reserves "memory bandwidth" run some 3D calculations much faster.
To connect video memory with extremely many signal lines on a GPU, the industry association JEDEC specifies the so-called Wide-I/O-Memory. The contact surfaces are on the DRAM, the positioned so that the memory chip is placed directly on the GPU, the leaves. The method has some drawbacks. One hand, the graphics chip - or the chip, which contains, inter alia, the GPU - now dissipate its heat through the resting memory chip through. On the other hand, the graphics memory can not be extended easily, it would be little-tested methods such as through-silicon vias (TSV) needed to approximately to the first DRAM grab the other can. The cooling problem is defused somewhat by the DRAM, the thin by grinding makes - in principle, it is possible the stack with 16 layers of 1.4 mm height to accommodate. Even the Hybrid Memory Cube (HMC) from Micron and Intel is designed as a 3D stack.
After an investigation by Chipworks is the Sony Wide-I/O-Konzept already in ARM SoC CXD5315GG for the Playstation Vita. Intel reportedly plans now for the first time, the stacks for x86 processors, namely for the Haswell CPUs with the GT3 variant of high-performance GPU. According to information from Charlie Demerjian of SemiAccurate.com is the code name for the stack Crystal Well. Some time ago had already been speculated that Intel is planning to use the stacking in the mass production.
The combination of CPU and RAM involves technical risks and makes the CPU manufacturers from another supplier dependent - the DRAM must be in the high quality and very precise execution be reliably available with rapidly growing demand. Common with ARM SoCs has therefore been a package-on-package (PoP) design where the SoC and DRAM in separate, preferably standardized enclosures stuck - and so are the requirements for joining technology is smaller and the suppliers can also switch from leicher . But the high number of contacts per PoP is hardly possible for Wide I / O, it goes up to 512 data signal lines. Could be a 4-gigabit chip (512 MB) about even with economical clock frequency of 1 GHz per DDR 128 GB of data per second to deliver.
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