Showing posts with label Processors. Show all posts
Showing posts with label Processors. Show all posts
Intel's Haswell GPU: Turbocharged and more Video Features
The integrated graphics units of the next-generation Core i processor Haswell will perform much better than their current Ivy Bridge predecessors, support DirectX 11.1 and bring a whole new set of video features. The Intel has been known in the IDF. The Haswell GPU will be available in three versions: GT1, GT2 and GT3. All versions are also universal calculations via OpenCL 1.2 capable - yet the Ivy Bridge GPUs support in conjunction with the Intel OpenCL 1.1 SDK only.
GT1 and GT2 have, according to the published architecture diagrams compared to Ivy Bridge GPU cluster with a second shader cores (execution units / ES). How much per block ES cluster Intel actually is unclear. Even more powerful GT3 should be by the second rasterizer and four instead of two shader clusters. These additional units may GT3 off idle, in order to minimize power consumption.
In addition to the shaders is also doubled the size of shared buffer memory and the number of texture units. This should handle certain texture formats up to four times faster than the Ivy Bridge GPUs called HD 2500 or HD 4000th
To the higher number of functional units on the GT3 fast enough to provide data, Intel has doubled the performance of most fixed-function units in the geometry of the 3D pipeline. These improvements also the variants GT1 and GT2 used to benefit. In addition, the command generator (Command Streamer) was complemented by a resource Streamer to feed the units more efficient and thus accelerate the rendering of 3D scenes.
Moreover, Intel leads the Video Quality Engine (VQE) as the sixth block of the GPU. She is responsible for the frame-rate conversion (frame rate conversion) and entwackelt videos. AMD Steady Video offers a similar feature since the year 2011 for Radeon graphics cards and processors APU combo. In addition, over VQE run some new features to beautify (HD) videos such as correcting skin tones and color gamut expansion.
Haswell hardware video transcoder Quick Sync to convert videos faster. The hardware decoder MFX also processes the Motion JPEG (MJPEG), as is common in conventional webcam sessions. Moreover MFX now encoded MPEG-2 content in real-time and decodes different video quality levels of a SVC stream (Scalable Video Coding). This is for professional video conferences with many participants thought of different bandwidths. As an innovation, Intel also praises the play of 4K x 2K Video. This should already dominate the Ivy Bridge MFX unit, which in our tests, but never worked.
Intel rumored to want the GT3 GPU also use Wide-I/O-Speicher that could increase the data transfer rate drastically.
Intel: "Reinventing Computing 'with Ultrabooks and x86 Tablets
Intel's CPO (Chief Product Officer) Dadi Perlmutter has opened this year's Developer Forum with a keynote entitled "Reinventing Computing". The apparent trend towards mobile devices, according to Perlmutter requires not only more energy-efficient processors, thus achieving long battery life, mobile devices, but also powerful servers in data centers, the mobile devices - legwork - from smartphones to the Internet of Things. Of course, he looks well placed for Intel, but the product portfolio ranges from small Atom Z2460 smartphone to server-processor Xeon Phi.
In general, he sees the trend towards mobile computing just beginning. The Ultrabooks play an important role, because they are supposed to fill the gap between tablet on one side and conventional laptop computer on the other. The concepts presented here and appliances were not new: Lenovo's Yoga notebook for example, was already demonstrated at CES in January, many others at Computex in June, or the recently concluded IFA.
Perlmutter did not specifically addresses the needs for future ultrabooks, but demonstrated the - mandatory with Haswell - Voice control for Ultrabooks. Nuance Dragon Assistant can pass queries, posting messages on Twitter or Facebook, and control music playback. A beta of Dragon Assistant should be completed in the fourth quarter, the final product Perlmutter introduced for the first quarter of 2013 in view. In addition to Ultrabooks can also be controlled with gestures, which Perlmutter vorführte the audience with a 3D webcam from Creative. The latter is strongly reminiscent of Microsoft's Kinect.
In addition, NFC are moving into Ultrabooks, which will allow some in conjunction with PayPass MasterCard's comfortable and secure Internet payments by credit card simply on the notebook sets, while walking in a shop at the virtual checkout. Perlmutter picked it out increased security because the background Intel IPT (Identity Protection Technology) cares for secure authentication of laptop and credit card over MasterCard's servers - without the traders have to change much on the payment process of their online shops.
Even with the tablet itself looks Intel is well positioned because soon stands at Clover Trail, the offshoot of the better tablet smartphone Atom processor Z2460 (Medfield). This means that (unlike Tablets with Core i processors) just as thin as possible without fans tablets with ARM processors, but unlike Windows RT it runs a full Windows 8 and therefore any x86 application. Performance miracles can be expected of course, and the demo tablets were found in Perlmutter's remarks still a bit square.
Perlmutter then gave an outlook for the coming generation Haswell processor and read the graphics benchmark Unigine run both on a current Ultrabook with Ivy Bridge processor as well as a reference system with Haswell processor. While the graphics stuttered at Ivy Bridge, it ran smoothly on Haswell - tessellation, however, was off on both systems. Conversely, should Haswell provide the same graphics performance as Ivy Bridge at much lower power consumption, which Perlmutter demonstrated also: Now stuttered image the same on both systems, but the Haswell system took it on only eight watts, while the Ivy Bridge processor full its 17 Watt TDP swallowed.
Finally gave Perlmutter also claims that PCs stuck into more and more, even where you do not expect it. Behind him like a vending machine was rolled onto the stage, which was equipped with a Core i7 and a 46-inch touchscreen. Perlmutter drew not only a drink, but then could also be photographed from the machine and send it through e-mail. The machine had no concept of the way, but is sold in South America.
Intel introduces Haswell processor
Outstanding here is the new active state power management "S0ix active idle", the down reduces energy consumption while doing nothing on the economical level of the sleep states S3 or S4, but does not require a long recovery time (Resume). All this is done automatically by hardware in fine-grained levels. There are also numerous improvements, both in the active state and in the S3/S4-Schlafzuständen. The CPU cores themselves offer for new C-States. The transition times were accelerated by 25 percent and the links to Periphie have new power management states. The platforms will display with Auto Refresh (PSR) have so that ultimately the power consumption can be reduced in idle to one-twentieth of the current values.
To increase the performance of Intel Haswell when compared to Ivy Bridge considerably knitted at the micro-architecture, but without changing the basic pipeline. Increases, the bandwidth to fetch the code, the branch prediction has been improved and enlarged the window for out-of-order. The L2 TLB is now slightly larger and optimized for large memory pages. Above all there were two additional ports that are served from the reservation station: Port 6 provides a fourth integer ALU and an additional branch unit. Port 7 controls to a dedicated store-address unit. The mighty AVX2 command for multiply-add (FMA) can be performed in parallel in two units via Port 0 and 1 with a latency of 5 cycles. In throughput Haswell comes with twice FMA at 32 flops per clock and core in single-precision and 16 flops / clock / core in the double precision, so it is likely the major Linpack benchmark at the same clock and the same number of nuclei twice the performance compared to the current Ivy Bridge reach.
That's enough alone to summon more functional units, the data must also be replenished fast enough. These Intel has doubled the L1 data and L2 cache throughput. The L1D can now read and write 64 bytes per clock (two AVX-words), and 32 bytes.
With the graphics Intel has the GT3 risen alongside numerous detail improvements, a second "wheel" to GT2: doubling the number of execution units (shaders), as well as units for rasterization, Z, stencil, color fade, and so on as well as the overall size of caches. The second disk can be turned off to save energy. The common "Not long" show part of the front pipeline sit include the Fix function units whose performance was doubled for most rendering tasks also. Finally, there is still the part of media, now offers the scalable video coding (SVC), and Motion-JPEG decoders. For MPEG2 can encode it on the fly, for example DLNA streaming and DVD production. It also now supports the playback of 4Kx2K video. While at Ivy Bridge, the individual engines could double work in parallel with the Haswell codec engines, imaging and scale / composite can now work in a triple parallel.
Intel promises next-generation Itanium still 2012
Intel will later this year introduce the new 32-nm variant "Poulson" Itanium CPU's. The current Itanium processor 9300 "Tukwila" dates from 2010. Intel countered by announcing rumors that CPU line would be discontinued. Rather, it is with "Kittson" continue the Poulson's successor in the planning.
Poulson and Kittson are announced for 2007. Regarding the expected as Intel Itanium 9500 Poulson had at ISSCC 2011 reveal a wealth of details: the chip with 3.1 billion transistors to eight multi-threaded cores, have a ring bus and 50 MB cache.
The largest customer for the 64-bit CPUs is co-developer Hewlett-Packard, which uses it in its high-end servers with the company's own operating system, HP-UX. The company had recently prevailed in a dispute with Oracle software to the Itanium. Oracle did not offer Itanium-based versions of its software more because it is in his opinion, is a dying art. HP did however find the court that it has a valid contract for the provision of Oracle software.
Intel is reportedly planning processors with integrated graphics memory
The performance of onboard graphics, today usually built right into the CPU is relatively small. Three major factors limit the GPU aka GPU: It may prove cost reasons only a certain portion of the total chip area, so it has fewer transistors than the GPU on a graphics card. Moreover, his thirst for power and capped it must share the main memory with the CPU cores and the PCI Express Root Complex.
Modern processors contain CPU and GPU cores, PCIe connectivity and memory controller. The latter controls often two each 8 bytes wide to DDR3-SDRAM channels with up to 800 MHz (DDR3-1600). Hence s data transfer rate of nearly 26 GB / High-end graphics chips for example, 256 data signal lines (32 bytes) to GDDR5 SDRAM, 2.5 GHz, data Read-/Write-Clock but with up to 160 GB / s read or write. Through these reserves "memory bandwidth" run some 3D calculations much faster.
To connect video memory with extremely many signal lines on a GPU, the industry association JEDEC specifies the so-called Wide-I/O-Memory. The contact surfaces are on the DRAM, the positioned so that the memory chip is placed directly on the GPU, the leaves. The method has some drawbacks. One hand, the graphics chip - or the chip, which contains, inter alia, the GPU - now dissipate its heat through the resting memory chip through. On the other hand, the graphics memory can not be extended easily, it would be little-tested methods such as through-silicon vias (TSV) needed to approximately to the first DRAM grab the other can. The cooling problem is defused somewhat by the DRAM, the thin by grinding makes - in principle, it is possible the stack with 16 layers of 1.4 mm height to accommodate. Even the Hybrid Memory Cube (HMC) from Micron and Intel is designed as a 3D stack.
After an investigation by Chipworks is the Sony Wide-I/O-Konzept already in ARM SoC CXD5315GG for the Playstation Vita. Intel reportedly plans now for the first time, the stacks for x86 processors, namely for the Haswell CPUs with the GT3 variant of high-performance GPU. According to information from Charlie Demerjian of SemiAccurate.com is the code name for the stack Crystal Well. Some time ago had already been speculated that Intel is planning to use the stacking in the mass production.
The combination of CPU and RAM involves technical risks and makes the CPU manufacturers from another supplier dependent - the DRAM must be in the high quality and very precise execution be reliably available with rapidly growing demand. Common with ARM SoCs has therefore been a package-on-package (PoP) design where the SoC and DRAM in separate, preferably standardized enclosures stuck - and so are the requirements for joining technology is smaller and the suppliers can also switch from leicher . But the high number of contacts per PoP is hardly possible for Wide I / O, it goes up to 512 data signal lines. Could be a 4-gigabit chip (512 MB) about even with economical clock frequency of 1 GHz per DDR 128 GB of data per second to deliver.
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